This invention relates to a circuit device for carrying out a hierarchic form of row decoding in semiconductor memory devices, and more particularly to a device which comprises at least one matrix of memory cells having sectors organized into colunmns, wherein each sector has a specific group of local word lines individually connected to a main word line running through all of the matrix sectors which have rows in common.
As is well known, a memory matrix architecture most widely utilized in the construction of semiconductor integrated, non-volatile memory devices is the NOR type.
In this type of architecture, memory cells belonging to one matrix row have their gate terminals in common, while memory cells belonging to one matrix column have their drain terminals in common. The source terminals are, on the other hand, shared by all the cells of one matrix sector. A portion of a NOR matrix is shown in FIG. 1 by way of example.
To specify a given memory location, it is sufficient to identify a given row and given column: one memory cell is to be found at their intersection.
As is known, in non-volatile memories, a memory cell comprises a floating-gate transistor which also has drain and source conduction terminals. Shown in FIG. 2 are examplary values of bias voltages to be applied to the terminals of a memory cell during read, write and erase operations, respectively.
A pre-requisite of non-volatile memories of the Flash EEPROM type is that the information stored therein should be erased as groups or packages of bits. The erase operation is the single operation that involves biasing of the source terminal, and since all the cells have this terminal in common, they can be written into and read from in an independent manner but must be erased simultaneously.
Particularly with Flash memories, the erase operation is performed by sectors, in the sense that all the cells that run to the same source line must be erased simultaneously.
Within a non-volatile memory matrix, the sectors can be organized either into rows or columns. In a row type of organization, the size of a sector is given by the number of rows that it contains. The architecture of the storage device is designed to suit the number and size of the sectors in order to optimize the circuit area consumption, as well as the device performance and reliability.
Since a single bit line to be shared by all of the matrix sectors would be impossible to provide due to a problem known as xe2x80x9cdrain stressxe2x80x9d, each sector is arranged to include a specific group of columns referred to as the xe2x80x9clocal bit linesxe2x80x9d. Local bit lines are individually connected, via a pass transistor, to a main metallization connection referred to as the xe2x80x9cmain bit linexe2x80x9d. Each sector is assigned a local group of pass transistors which are only turned on in the addressed sector, so that the cells of the other matrix sectors need not be affected by drain stress.
Shown schematically in FIG. 3 is a conventional architecture for a non-volatile memory matrix wherein the sectors are organized into rows. Also shown therein are the various row decoders associated with each sector.
Such an architecture islarge in circuit space requirements because it entails the provision of a decoder for each sector, and of local column decoders to avoid the drain stress phenomenon.
Furthermore, it should be noted that the rows of the memory matrix are physically in the form of polysilicon strips interconnecting all the gate terminals of the cells in one row.
From an electrical standpoint, each polysilicon strip may be viewed as a distributed RC network. For example, even when a relatively small number of cells such as 1024 is assumed, the time constant associate with one row in the matrix and defined by the RC network would be approximately 10 nsec. This value represents the time interval to be allowed for an electric signal to go through a matrix row, and it affects the memory access time directly which, as can be appreciated, should be kept as short as possible.
Due to the high cell integration density in the integrated storage circuit, the local bit lines and main bit line are formed by a process which results in two different metallization layers or levels being deposited, and unless a third metallization level is provided, the polysilicon row cannot be short-circuited and the row charging time be reduced.
Another prior technical solution provides non-volatile memory matrices which are organized into columns. In this case, the matrix rows are shared in common by all sectors, and the sector size is determined by the number of columns. FIG. 4 is a schematic view of a portion of a memory matrix organized into columns.
With this type of architecture, the parasitic capacitance of each bit line can be kept quite low, which is beneficial to the circuit portion involved in reading the memory contents. In addition, row decoding will be shared by several matrix sectors, which affords savings in circuit space.
Where a matrix is fabricated by a technological process providing two metallization levels, one level is used for forming the bit lines, and the other level is used for short-circuiting the row in order to reduce its parasitic resistance during the charging phase.
While being advantageous in several ways, the last-mentioned architecture has a drawback in that, each time that a cell is addressed, all the cells in the same row also become biased and affected by the so-called xe2x80x9cgate stressxe2x80x9d.
Consistently with a current trend in Flash storage devices provided with a single supply voltage, the erasing phase is performed by sectors, with the gate terminals of the cells being biased with negative voltages. The negative gate erase mode used for matrices having sectors organized into columns results in an unacceptable amount of gate stress for the memory device.
Embodiments of this invention provide a circuit device which allows negative voltage erasing in memory matrices that are organized into columns, thereby overcoming the limitations and drawbacks of prior art solutions for non-volatile memory devices having a single-voltage supply.
One of the principles on which embodiments of the present invention stand is one of performing a row decoding phase of the hierarchic type by means of an additional transistor having conduction terminals connected, one to the local word line and the other to a ground reference voltage.
In one embodiment, a circuit device is provided capable of carrying out a hierarchic form of row decoding for semiconductor memory devices of the non-volatile type comprising at least one matrix of memory cells with sectors organized into columns, where each sector has a specific group of local word lines individually connected to a main word line running through all of the matrix sectors which have rows in common. The device includes a first transistor having conduction terminals connected between the main word line and the local word line, and a second transistor having its conduction terminals connected between the local word line and a reference voltage.